A key metric for performance of transistors is the on-current, which is the current of a transistor per unit gate width when it is turned on. The on-current may be altered by changes in the band structure of the semiconductor substrate on which the transistor is formed. While the nature of stress needed to increase the on-current of a transistor may be dependent on the semiconductor substrate and the type of the transistor, in general, the band structure of a semiconductor device may be altered to increase the mobility of charge carriers, i.e., electrons or holes. For example, by manipulating transistor structures such that a favorable type of stress is applied to each type of transistors, both P-type field effect transistors (PFETs) and N-type field effect transistors (NFETs) with enhanced minority carrier mobility may be formed in a CMOS transistor device.
Particularly, the electron mobility and the on-current are increased on an NFET formed on a silicon substrate if the channel of NFET is under a tensile uniaxial stress in the direction of the current flow in the channel. Likewise, the hole mobility and the on-current are increased for a PFET formed on a silicon substrate if the channel of PFET is under a compressive uniaxial stress in the direction of the current flow in the channel. Structures, known in the art, for applying stress to the channel of a field effect transistor include a strained semiconductor substrate, stress liners, and stress-generating embedded source and drain semiconductor materials.
According to the prior, stress applied to the channel of a MOSFET is generated by a stress liner surrounding a gate electrode. The stress liner is of unitary construction around the gate electrode and surrounds the gate spacer, which surrounds the gate electrode. Typically, the stress liner contacts the entire outer sidewalls of the gate spacer and applies either a compressive stress or a tensile stress to the gate spacer. The stress applied to the gate spacer is transmitted to the gate electrode and to the channel of the MOSFET. In general, the higher the stress, the greater the modification to the band structure and the change to the mobility. Stress liners are typically silicon nitrides formed by plasma enhanced chemical vapor deposition (PECVD) or high density plasma chemical vapor deposition (HDPCVD). Stress liners that can apply a high compressive or tensile stress of 2˜3 GPa in magnitude to the channel of the MOSFET are known in the art.
The stress generated by the stress liners is typically distributed over the gate electrode and the channel. Since the band structure of the channel is entirely determined by the stress of the channel, but is independent of the stress on the gate electrode, the stress applied to the gate electrode does not enhance the mobility of the charge carriers. The level of stress that a particular type of stress liner can generate is limited by intrinsic properties of the stress liner. Yet, an even higher level of stress on the channel is desired to enhance the mobility of charge carriers in the channel.
Therefore, there exists a need to increase the stress on the channel of a MOSFET through more effective use of the stress generated by stress liners.
Specifically, there exists a need for a semiconductor structure that more effectively transmits the stress that is generated by a stress liner to the channel of the MOSFET and methods of manufacturing the same.